Logic gates and switches with Ioff or powered-off protection: empowering you to power down - Analog - Technical articles - TI E2E support forums
Analysis of a Parasitic‐Diode‐Triggered Electrostatic Discharge Protection Circuit for 12 V Applications - Song - 2017 - ETRI Journal - Wiley Online Library
30 Parasitic diodes and BJTs in CMOS processes - YouTube
ESD Device Modeling: Part 1 - In Compliance Magazine
Low-C ESD Protection Design in CMOS Technology | IntechOpen