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The following logic gate circuit is equivalent to:\n \n \n \n \n (A) NAND gate(B) OR gate(C) XOR gate(D) NOT gate
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 \\[A \\](https://www.vedantu.com/question-sets/0aac9364-89e1-4fe2-b20a-a51fa1bbca101855660548264705312.png "The diagram of the logic gate circuit is given below. The output Y of the circuit is represented by\n \n \n \n \n (A) \\[A \\cdot \\left( {B + C} \\right)\\](B) \\[A \\")
The diagram of the logic gate circuit is given below. The output Y of the circuit is represented by\n \n \n \n \n (A) \\[A \\cdot \\left( {B + C} \\right)\\](B) \\[A \\
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